1. Field of the Invention
The present invention relates to a liquid crystal display control device which is used to reduce the storage capacity of a storage element required when an image formed from video signals transmitted from a personal computer or the like is displayed in an enlarged mode on a liquid crystal display device.
2. Description of Related Art
A technique as disclosed in Japanese Laid-open Patent Application No. Hei-4-12393 has been known as a liquid crystal display control device for displaying video information from a personal computer or the like while enlarging the video information. In this technique, a video signal transmitted from a personal computer or the like is temporarily stored in a frame memory, and the stored data are read out at a timing which is compatible with a liquid crystal display operation. This technique will be described in detail with reference to FIGS. 12 and 13.
FIG. 12 is a block diagram showing a control circuit in a liquid crystal display device disclosed in Japanese Laid-open Patent Application No. Hei-4-12303. In FIG. 12, reference numeral 1101 represents a video signal from the personal computer or the like, and reference numeral 1102 represents a synchronous signal. Reference numeral 1103 represents a horizontal/vertical timing and basic clock generating circuit, reference numeral 1104 represents an automatic input signal discriminant circuit, reference numeral 1105 represents a frame memory data generating and frame memory write-in circuit, reference numeral 1106 represents a frame memory circuit which comprises a field memory and a line buffer, reference numeral 1107 represents a frame memory read-out and display data generating circuit, reference numeral 1108 represents an enlarged display control circuit, reference numeral 1109 represents a liquid crystal display circuit, and reference numeral 1110 represents a liquid crystal display unit.
FIG. 13 is a block diagram showing the details of the frame memory circuit 1106 shown in FIG. 12. In FIG. 13, reference numeral 1201 represents a field memory, reference numeral 1202 represents a line buffer and reference numeral 1203 represents a read-out data select circuit.
In FIGS. 12 and 13, the horizontal/vertical timing and basic clock generating circuit 1103 generates a horizontal timing signal, a vertical timing signal and a basic clock signal CK1 for controlling the operation of the frame memory data generating and frame memory write-in circuit 1105 on the basis of the horizontal and vertical synchronous signals 1102 for driving a CRT display device which are input from the personal computer or the like.
The frame memory data generating and frame memory write-in circuit 1105 generates a control signal WRCT (write clock signal SWCK, write enable signal WE, reset write signal RSTW) on the basis of the basic clock signal CK1, and outputs the control signal WRCT to the field memory 1201 (see FIG. 13). Further, using the frame memory data generating and frame memory write-in circuit 1105, memory data Din of one frame which are generated on the basis of the video signal 1101 input from the personal computer or the like are successively written and temporarily stored into the field memory 1201.
Furthermore, the frame memory read-out and display data generating circuit 1107 generates a control signal RDCT on the basis of the clock signal CK2 for driving the liquid crystal display, generated by the liquid crystal display circuit 1109, and the control signal generated by the enlarged display control circuit 1108, and then outputs the control signal RDCT to the frame memory circuit 1106. The clock signal CK2 for driving the liquid crystal display is set to have a longer period than the basic clock signal CK1.
The control signal RDCT comprises a read clock signal SRCK, a read reset signal RSTR, a write clock signal WCK, a reset write signal RSTWN, a read clock signal RCK, a reset read signal RSTRN and a data selection signal SELDT. Of these signals, the read clock signal SRCK and the read reset signal RSTR are supplied to the field memory 1201. The write clock signal WCK, the reset write signal RSTWN, the read clock signal RCK and the reset read signal RSTRN are supplied to the line buffer 1202 of the frame memory circuit 1106. The data selection signal SELDT are supplied to the read-out data select circuit 1203 of the frame memory 1106.
The read-out data select circuit 1203 selects any one of an output data D1 of the field memory 1201 and an output data D2 of the line buffer 1202, and outputs the selected data as frame memory read-out data Dout.
On the basis of the data Dout, the frame memory read-out and display data generating circuit 1107 as described above generates serial liquid crystal display data which are compatible with the liquid crystal display unit 1110.
On the basis of the clock signal CK2 for driving the liquid crystal display, the liquid crystal display circuit 1109 generates a liquid crystal display driving signal, a data shift clock signal and an alternating signal which are compatible with the format of the liquid crystal display unit 1110.
The liquid crystal display unit 1110 displays a predetermined image on the basis of the liquid crystal display data output from the frame memory read-out and display data generating circuit 1107 and the signal output from the liquid crystal display circuit 1109.
The enlarged display control circuit 1108 judges whether an instruction for enlarging a part of the frame is made by an operator. If it is judged that the enlarge display instruction is made, it controls the frame memory data generating and frame memory write-in circuit 1105 and the frame memory read-out and display data generating circuit 1107 in accordance with information on an indicated magnification rate, an enlarging area, etc.
Further, the automatic input signal discriminant circuit 1104 discriminates, on the basis of the synchronous signal 1102, an input video signal which is varied in accordance with, for example, the type of personal computer, and it controls the horizontal/vertical timing and basic clock generating circuit 1103 in accordance with the discrimination result.
According to the above-described technique, the enlargement processing can be performed. However, since the input and output operations of the video signals are perfectly asynchronously controlled by using a field memory, the field memory must have a storage capacity for storing video information of at least one frame. The memory capacity in which the video information of one frame can be stored is not so small in the present memory technique.
Furthermore, in the conventional technique as described above, all video signals are temporarily stored in the frame memory circuit 1106 so as to keep the read-out timing to the liquid crystal display unit constant at all times. Therefore, when a high-resolution video signal is input, a field memory to which high-speed access can be made is required irrespective of use and non-use of the enlargement processing. The use of a memory which can be accessed at high speed is a factor preventing cost reduction of the display device, because such a memory is expensive.
An object of the present invention is to provide a liquid crystal display control device which performs enlargement processing while suppressing increase in memory capacity.
Another object of the present invention is to provide a liquid crystal display control device which enables application to high-resolution video signals irrespective of use of a memory having a low access speed (i.e., a cheap memory).
A further object of the present invention is to provide a liquid crystal display control device which can freely select any image quality and any cost in accordance with a user""s request.
In order to attain the above objects, according to a first aspect of the present invention, a liquid crystal display control device for receiving an input video signal and outputting display data corresponding to the video signal to a liquid crystal display panel to display the picture of the display data on the liquid crystal display panel, comprises a storage element for storing the input video signal, and memory control means for controlling the storage element to store the input video signal at the timing corresponding to the input timing of the video signal and to read out the video signal from the storage element at the timing corresponding to the output timing of the display data to the liquid crystal display panel.
Now, the operation of the first aspect of the present invention will be described. The memory control means controls the video signal input from a personal computer or the like to be stored into the storage element at the timing corresponding to the input timing of the video signal. In addition, at the same time, the memory control means controls the video signal to be read out from the storage element at the timing corresponding to the output timing of the display data to the liquid crystal display panel. Accordingly, the storage element may be designed to have a storage capacity of only two lines.
According to a second aspect of the present invention, a liquid crystal display control device for receiving an input video signal and displaying a picture corresponding to the video signal on a liquid crystal display, comprises a frame memory for storing the input video signal, a line memory for storing a video signal read out from the frame memory, memory control means for controlling the data write-in and read-out operation of the video signal in and from the frame memory and the line memory, and a calculation processing circuit for performing predetermined processing on the video signal read out from the frame memory and the video signal read out from the line memory, and then outputting the processed video signals to the liquid crystal display panel, wherein the memory control means synchronizes the read-out of the video signal from the frame memory and the write-in of the video signal into the frame memory every time interval which is determined separately.
In this case, it is preferable that the frame memory has a storage capacity corresponding to two lines of the input video signal.
Now the operation of the second aspect of the present invention will be described. The memory control means controls the video signal input from a personal computer or the like to be read out from the frame memory. In this case, the memory control means causes the read-out operation to be synchronized to the write-in operation of the video signal into the frame memory every time interval which is determined separately (the synchronization does not used to be established at all times). Accordingly, it is sufficient for the frame memory to have a storage capacity of only two lines.
The calculation processing circuit performs predetermined processing (for example, enlargement processing) on the video signal read out from the frame memory and the video signal read out from the line memory, and then outputs the processed signals to the liquid crystal display panel. When the predetermined processing is enlargement/reduction processing, the separately-determined time interval is set in accordance with the enlargement/reduction rate.
If the frame memory and the line memory are constructed by a single kind of storage element, this is convenient from the standpoint of the simplicity of the device. According to the present invention, it is necessary to control the input and output operations asynchronously and to perform the input and output operations at the same time. Accordingly, a FIFO type line buffer is most preferable as a storage element being used in this embodiment (the same is true for other embodiments). If the input video signal is processed in two-parallel mode, the frame memory may be constructed using a FIFO type line memory having a storage capacity of one line in an expansion direction. With this construction, the data amount which can be processed within a unit time is doubled, and thus the data processing speed is enhanced.
According to a third aspect of the present invention, a liquid crystal display control device for receiving an input video signal and displaying a picture corresponding to the video signal on a liquid crystal display panel, comprises a frame memory for storing the input video signal, a memory mount portion for being capable of mounting thereon a line memory which is separately provided to store a video signal read out from the frame memory, memory control means for controlling an input/output operation of the video signal to/from the frame memory and an input/output operation of the video signal to/from the line memory mounted on the memory mount portion, and a calculation processing circuit for performing predetermined processing on the video signal read out from the frame memory or the video signals read out from both the frame memory and the line memory mounted on the memory mount portion, and then outputting the processed signal(s) to the liquid crystal display panel.
In this case, the calculation circuit is preferably designed to change its processing content in accordance with the presence or absence of the line memory (i.e., the situation where the line memory is provided or not). The memory mount portion is preferably designed so that a memory card can be mounted on the memory mount portion. Further, the processing which is performed by the calculation processing circuit may contain the enlargement/reduction processing of the picture corresponding to the video signal.
Now the operation of the third aspect of the present invention will be described. The memory control means controls the input/output of the video signal to/from the frame memory, the line memory mounted the memory mount portion (it may be formed as a memory card). The calculation processing circuit performs the predetermined processing (for example, the enlargement/reduction processing of the picture corresponding to the video signal) on the video signal which is read out from the frame memory and the line memory mounted on the memory mount portion, and then outputs the processed signal to the liquid crystal panel. The calculation processing circuit changes its processing content in accordance with the presence or absence of the line memory. Accordingly, the system can be constructed so as to meet the image quality which is desired by a user and at a permissible cost in accordance with the situation where the line memory is provided or not.
According to a fourth aspect of the present invention, a liquid crystal display control device for receiving an input video signal and displaying the picture corresponding to the video signal on the liquid crystal display panel, comprises resolution judgment means for judging the resolution of the input video signal, first processing means for directly outputting the video signal as a bypass video signal, second processing means for performing predetermined processing on the input video signal and then outputting the signal as a processed signal, and timing adjusting means for adjusting an output timing of the signal output from the first processing means or the second processing means to the liquid crystal display panel, wherein the first processing means outputs the bypass video signal when a resolution of the video signal which is judged by the resolution judgment means is coincident with the resolution of the liquid crystal display panel, and stops the output of the bypass video signal when the resolution of the video signal which is judged by the resolution judgment means is not coincident with the resolution of the liquid crystal display panel, and wherein the second processing means stops the output of the processed signal when the resolution of the video signal which is judged by the resolution judgment means is coincident with the resolution of the liquid crystal display panel, and outputs the processed signal when the resolution of the video signal which is judged by the resolution judgment means is not coincident with the resolution of the liquid crystal display panel.
In this case, the second processing means may perform the enlargement processing on the video signal.
Now the operation of the fourth aspect of the present invention will be described. The resolution judgment means judges the resolution of the input video signal. The first processing means and the second processing means change their processing operations in accordance with the resolution judgment results. That is, when the resolution of the video signal which is judged by the resolution judgment means is coincident with the resolution of the liquid crystal display panel, the first processing means outputs the bypass video signal. On the other hand, the second processing means stops the output of the processed signal. Conversely, when the resolution of the video signal which is judged by the resolution judgment means is not coincident with the resolution of the liquid crystal display panel, the second processing means performs the predetermined processing (for example, picture enlargement processing) on the input video signal, and then outputs the signal as a processed signal. On the other hand, the first processing means stops the output of the bypass video signal. The timing adjusting means adjusts the timing of the signal which is output from the first processing means or the second processing means, and then outputs the timing-adjusted signal to the liquid crystal display panel.
As described above, the processing means (or processing route) of video signals is switched in accordance with the resolution. Thus, means which is applicable to any resolution is not required to be used as an element constituting each processing means. For example, when the second processing means performs the enlargement processing or the like by using a frame memory or the like, the second processing means is not required to have the capability of processing the video signals of the same high resolution as the liquid crystal panel. Accordingly, a memory having a low access speed and a low price may be used as the frame memory of the second processing means.
As described above, according to the present invention, the enlargement display of video signals on the liquid crystal display panel can be performed by using a memory of low access speed and low price (for example, FIFO type line buffer).
Furthermore, an enlargement processing method can be freely selected in accordance with the presence or absence of a line memory. Therefore, a user can select any suitable device construction in accordance with an application, a cost and image quality requested by the user.